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march 2011 doc id 11165 rev 5 1/33 AN2115 application note designing an application with the l6928, high efficiency monolithic synchronous step-down regulator introduction this application note details the main features and application advantages of the l6928. after describing how the device works and its main features, a step-by-step design section is provided to aid in the selection of the external components and evaluation of the losses. the performance of the l6928 is expressed in terms of efficiency and thermal results. at the conclusion of this document a few application ideas are provided. figure 1. minimum application board size www.st.com
contents AN2115 2/33 doc id 11165 rev 5 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 light load modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.1 low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 system stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.1 current loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.2 voltage loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 dropout operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 pgood (power good output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 ovp (overvoltage protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.5 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 external component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.1 input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.2 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1.3 inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1.4 compensation network (r1 c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 application losses and efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.1 conduction losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.2 switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.3 gate charge losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.4 thermal consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
AN2115 contents doc id 11165 rev 5 3/33 7 application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.0.1 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 efficiency results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 buck boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 white leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2.1 driving white leds: buck topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.2 driving white leds: boost topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.2.3 driving white leds: buck boost topology . . . . . . . . . . . . . . . . . . . . . . . . 30 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
list of tables AN2115 4/33 doc id 11165 rev 5 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. minimum inductor value to ensure loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. recommended input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 table 4. recommended output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. recommended inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. demonstration board parts list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AN2115 list of figures doc id 11165 rev 5 5/33 list of figures figure 1. minimum application board size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. minimum size application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. equivalent circuit for voltage loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10. equivalent buck converter circuit (during on time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. equivalent buck converter circuit (during off time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. valley current limit intervention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. thermal performance results: v in = 3.7 v, v out = 1.8 v, i out = 800 ma . . . . . . . . . . . . . 22 figure 14. r ds(on) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 15. component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16. top side view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17. bottom side view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18. schematic of the demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 figure 19. low noise vs. low consumption efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20. efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 21. efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 22. efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. positive buck boost application. 1 li-ion cell to 3.3 v@0.25 a. . . . . . . . . . . . . . . . . . . . . . 28 figure 24. buck led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 25. boost led. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 26. buck boost led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 27. led dimming control using pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 28. analog led dimming control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
device description AN2115 6/33 doc id 11165 rev 5 1 device description the l6928 is a high efficiency monolithic synchronous step-down regulator capable of delivering up to 800 ma at output voltages from 0.6 v to v in (100% duty cycle). it has been designed using bcdv technology and employs a constant frequency peak current mode as the control loop architecture. the input voltage ranges from 2 v to 5.5 v. thanks to very low quiescent current (25 a) and shutdown current (0.2 a), the device is highly suitable for supplying battery-powered equipment (particularly for those using single lithium-ion cells) such as pdas and hand-held terminals, dscs (digital still cameras) and cellular phones. while the switching frequency is internally set at 1.4 mhz, the device can be externally synchronized from 1 mhz to 2 mhz. if this feature is not required, it can operate in low consumption mode (lcm) or low noise mode (lnm), depending on the sync pin value. a very low internal reference voltage (0.6 v typ.) allows the device to regulate very low output voltages, in accordance with new microprocessor supply voltage requirements. the very low r ds(on) of the power mosfets ensures high efficiency at high output current. other beneficial features are uvlo (undervoltage lockout), ovp (overvoltage protection), constant current short circuit protection, power good (power good output) and thermal shutdown. the space saving msop8 package, combined with a minimum need for external components, allows for very compact applications. figure 2. minimum size application circuit figure 3. pin connection figure 4. package run comp vfb gnd 1 3 2 v cc sync pgood 8 7 6 5 d01in1239amod 4
AN2115 pin function doc id 11165 rev 5 7/33 2 pin function table 1. pin description pin n name description 1 run shutdown input. when connected to a low leve l voltage (less than 0. 5 v) the device stops working. when high (above 1.3 v) the device is enabled. this pin must not be left floating. 2 comp error amplifier output. a compensation network must be connected to this pin. usually a 220 pf capacitor is sufficient to guarantee loop stability (see related section). 3 vfb error amplifier inverting input. the output voltage can be adjusted by connecting this pin to an external resistor divider from 0.6 v up to the input voltage. 4 gnd ground. 5 lx switch output node. this pin is internally c onnected to the drain of the internal switches. 6 vcc input voltage. the start-up input voltage is 2.2 v (typ.) while the operating input voltage ranges from 2 v to 5.5 v. an internal uvlo circuit generates a 200 mv (typ.) hysteresis. 7 sync operating mode selector input. when high (above 1.3 v) low consumption mode is selected. when low (less than 0.5 v), low noise mode is select ed. if connected to an appropriate external synchronization signal (from 1 mhz up to 2 mhz) the internal synchronization circuit is activated and the device works at the same switching frequency. this pin must not be left floating. 8 pgood power good comparator output. it is an open dr ain output. a pull-up resistor should be connected between pgood and v o (or v cc depending on the requirements). the pin is forced low when the output voltage is lower than 90% of the regulated output voltage, and goes high when the output voltage is greater than 90% of th e regulated output voltage. the pin can be left floating if not needed.
block diagram AN2115 8/33 doc id 11165 rev 5 3 block diagram figure 5. block diagram
AN2115 operation description doc id 11165 rev 5 9/33 4 operation description the main loop uses a constant frequency peak current mode architecture. each cycle, the high side mosfet is turned on, triggered by the oscillator, so that the current flowing through it (which is the same as the inductor cu rrent) increases. when this current reaches the threshold (set by the output of the error amplifier e/a, the peak current limit comparator, peak_cl, turns off the high side mosfet and turns on the low side mosfet until the next clock cycle begins, or if the current flowing through it decreases to zero (zero crossing comparator). in particular, the error amplifier output is dependent on the fb pin voltage. when the output current increases, the output capacitor is discharged and so the fb pin voltage decreases. this produces an increase in the error amplifier output, allowing a higher value for the peak inductor current. for the same reason, when the output current decreases due to a load transient, the error amplifier output goes low, thus reducing the peak inductor current to meet the new load requirements. the system includes a slope compensation sign al, added to the sensed high side ramp current, which provides loop stability even in high duty cycle conditions (see related section). 4.1 light load modes of operation depending on the sync pin value, the device can operate in lcm (low consumption mode) or lnm (low noise mode). if the sync pin is high (greater than 1.3 v) low consumption mode is selected while low noise mode is selected if the sync pin is low (less than 0.5 v). 4.2 low consumption mode in this mode of operation, the device oper ates discontinuously based on the comp pin voltage in order to maintain very high efficiency even in light load conditions. when the device is not switching, the load discharges the output capacitor and the output voltage decreases. when the feedback voltage goes below the internal reference, the comp pin voltage increases, and when an internal threshold is reached the device begins to switch. in this condition the peak current limit is set in the range of approximately 200 ma - 400 ma, depending on the slope compensation (see related section). once the device starts to switch, the output capacitor is recharged. the feedback pin voltage increases and, when it reaches a value slightly higher than the reference voltage, the output of the error amplifier decreases until a clamp is activated. at this point the device stops switching. in this phase, most of the internal circuitry is off, reducing the device?s consumption down to a typical value of 25 a. 4.2.1 low noise mode if for noise considerations, the very low frequencies of low consumption mode are undesirable, low noise mode can be selected. in low noise mode, efficiency is slightly lower compared to low consumption mo de in very light load conditi ons, but for medium-high load currents the efficiency values are very similar.
operation description AN2115 10/33 doc id 11165 rev 5 basically, the device switches with its internal free running frequency of 1.4 mhz. obviously, in very light load conditions, the device could skip some cycles in order to keep the output voltage regulated. in figure 6 and figure 7 the lcm and lnm typical waveforms are shown. figure 6. low consumption mode figure 7. low noise mode measurement conditions: ?v in = 4.2 v ?v out = 1.5 v ?i out = 30 ma ? l = 3.3 h ?c in = 10 f ?c out = 10 f ?r c = 20 k ?c c = 330 pf a comparison between the efficiency in low noise mode and low consumption mode is shown in figure 19 of this document. red line: inductor current blue line: output voltage (ac coupled) green line: lx pin red line: inductor current blue line: output voltage (ac coupled) green line: lx pin
AN2115 operation description doc id 11165 rev 5 11/33 4.3 system stability since the device is designed with a current mo de architecture, loop stability is rarely a significant issue. for most applications a 220 pf capacitor connected between the comp pin and ground is sufficient to guarantee stability. if very low esr capacitors are used for the output filter, such as multilayer ceramic capacitors, the zero introduced by the capacitor itself can shift at very high frequency and the transient loop response could be affected. adding a series resistor to the 220 pf capacitor may resolve this problem. the appropriate value for the resistor (in the range of 50 k ) can be determined by checking the load transient response of the device. basically, the output voltage should be checked with an oscilloscope after the load steps required by the application. if there are stability problems, the output vo ltage could oscillate before reaching the regulated value after a load step. the curr ent mode stability can be observed in two consecutive steps: first, the inner (current) loop is closed, then the second (voltage) loop stability is considered. 4.3.1 current loop compensation the constant frequency, peak current mode control architecture offers numerous advantages: easy compensation with ceramic output capacitors, fast transient response and intrinsic peak current measurement which simplifies the current limit protection. one drawback, however, is that the current loop becomes unstable when the duty cycle exceeds 50%. this phenomenon is known as "sub-harmonic oscillation" and can be avoided by adding an external ramp to the one coming from the sensed current (or, by subtracting it from the control value, which is the e/a output voltage). this additional ramp is called "slope compensation". in the l6928 the slope compensation is implemented from a duty cycle of around 25% - 30%, as shown in figure 8 . figure 8. slope compensation the figure above shows that th e current limit value will depen d on the duty factor, so changing the output vo ltage will also change th e maximum output load. the amount of slope compensation depends on the inductor current slope during the off time. this slope, for a given duty cycle, is inversely proportional to the inductor value.
operation description AN2115 12/33 doc id 11165 rev 5 since the device can be synchronized at a higher frequency, the inductor value can be adjusted based on this. in fact, for a given current ripple, the required inductor value is inversely proportional to the frequency. finally, the input voltage affects the off time slope as well. this is obvious because, for a given duty cycle, the output voltage (and thus the off time inductor current slope) is directly proportional to the input voltage. in order to better manage these issues, the amount of slope compensation in the l6928 depends both on the switching frequency and input voltage. in the table above the minimum inductance valu es to ensure current loop stability with input voltage of 3.3 v and 5 v are shown. there is also a maximum inductor value, because if the inductor is too high the inductor current ripple will be very low (theoretically down to zero) and will be compared with the slop e compensation (a triangular waveform) to generate the duty cycle. this system is similar to the vo ltage mode control causin g stability problems due to the lc double pole (the pole splitting effect will not be present). 4.3.2 voltage loop compensation after closing the current loop, the pole splitti ng effect will separate the complex double pole, due to the inductor and the output capacitor, into 2 separate poles. the pole due to the inductor will shift outside of the system bandwidth (i.e. the induc tor ideally acts like a current source), while the pole due to the output capacitor will re main within the bandwidth. figure 9 shows the equivalent circuit used to study the voltage loop compensation: table 2. minimum inductor value to ensure loop stability v in [v] v out [v] f sw [khz] minimum inductor value [h] 3.3 1.8 1000 1.0 2000 1.0 53.3 1000 2.2 2000 2.2
AN2115 operation description doc id 11165 rev 5 13/33 figure 9. equivalent circuit for voltage loop analysis to complete the power stage analysis, the zero due to the output capacitor esr should be considered. equation 1 in equation 1 the power stage transfer function is shown, where ro is the output equivalent resistor load (v o /i o ). it can be observed that the pole due to the output capacitor shifts in frequency based on the load value. in order to have zero dc error regulation, the feedback voltage loop is implemented with an integrator stage, the transfer function of which is shown in equation 2 . equation 2 where g m is the integrator transconductance (250 s). the total gain loop is: equation 3 where a v is the current loop factor (1 typ.) and is the resistor feedback network partition (r 2 /(r 2 +r 3 ). equation 3 does not consider the poles due to the sampling effect which are placed at half of the switching frequency. once the gain loop is known, the system will be stabilized with the compensation network as shown in the section 6.1.4 . hs () v o s () i l s () -------------- - sc o esr 1 + () r o sc o esr r o + () 1 + --------------------------------------------------- - = = gs () g m a v ----------- sc c r c 1 + sc c ---------------------------- - ?? ?? ? = g loop s () r o g m 1sesrc o + () sc c r c 1 + () a v sc c 1sc o esr r o + () + () ------------------------------------------------------------------------------------------- - =
operation description AN2115 14/33 doc id 11165 rev 5 4.4 short circuit protection due to the peak current mode architecture, the peak current flowing through the high side switch is accurately sensed. when this current reaches the peak current limit threshold, the p-channel mosfet is turned off. in this way, the on time of the high side switch, t on , is reduced and the output voltage decreases. the t on can decrease down to its minimum value of around 200 nsec (t min ). in this condition, however, a strong overload or short circuit could result in a further increase in peak current. equation 4 equation 5 it can be observed in the equations above that in short circuit condition the output voltage is zero and thus the negative slope will be zero . since the positive slope increases with every cycle, the inductor current will lik ewise increase cycle by cycle. in order to determine at what point this phenomenon will ce ase, some real parameters should be considered. figure 10. equivalent buck converter circuit (during on time) figure 11. equivalent buck converter circuit (during off time) considering the figures above, particularly during off time, even though the output voltage is equal to zero, the output current generates the voltage drop necessary to produce a negative slope on the parasitic resistances. i on v in v out ? () l ------------------------------ t on ? = (positive slope) i off v out l ---------- - t off ? = (negative slope)
AN2115 operation description doc id 11165 rev 5 15/33 so the higher the output current, the higher the negative slope during off time. in this way the inductor current will find a stable find va lue, which can be deriv ed using the equation below: equation 6 where t min is the minimum on time, f sw is the switching frequency, r n and r p are the on resistances of the n-channel and p-channel mosfets respectively, r l is the inductor series resistance and r o is the equivalent output resistance. as can be observed, under these extreme conditions the maximum current value depends on both the application conditions (such as v in and f sw ) as well as the inductor parasitic resistor r l and the mosfets? r ds(on), r n and r p . the maximum current value does not depend on the peak current limit at all. in order to limit the output current to a safe value even in extreme short circuit conditions, a current limit has also been introduced on the n-channel mosfet, which operates as a valley current limit. figure 11 shows its operation. the p-channel mosfet does not turn on until the inductor current exceeds the valley current limit. this implies that the device skips some cycles depending on the overcurrent conditions, reducing the equivalent switching frequency in order to limit the output current. with this approach, the maximum peak current is definitively limited to: equation 7 figure 12. valley current limit intervention i lim v in t min f sw ? () ? r n r l + () 1t min f sw ? ? () r p r l + () t min f sw ? () ? + ? [] ------------------------------------------------------------------------------------------------------------------------------- ---------------------------- = i lim i valley v in t min l --------------------- + =
synchronization AN2115 16/33 doc id 11165 rev 5 5 synchronization the device can also be synchronized with an external signal from 1 mhz up to 2 mhz through the internal pll. when the device is locked, the external signal and the high side turn on rising edges are aligned. in this ca se, low noise mode is automatically selected. the device could skip some cycles in very light load conditions depending on the input/output conditions. the internal synchronization circuit is inhibited in short circuit and overvoltage conditions in order to keep the protections effective (see relative sections). the synchronization signal amplitude can range typically from 1 v to v cc and the duty factor can range typically from 20% to 80%. occasionally, if the synchronization signal duty cycle is very similar to the application duty factor, a jittering can be detected on the lx pin. in this case some practical solutions are listed below: 1. change the synchronization signal duty factor. 2. decrease the synchronization signal amplitude. 3. add a 20 pf capacitor between the comp pin and ground. the device switches at 1.4 mhz (typ.) if no synchronization signal is applied. 5.1 dropout operation the li-ion battery voltage ranges from approximately 3 v to 4.2 v (depending on the anode material). if the regulated output voltage is from 2.5 v and 3.3 v, it is possible for the battery voltage to decrease to the regulated voltage near the end of battery life. in this case, the device stops switching and works at 100% of duty cycle, minimizing the dropout voltage and the device losses. the minimum input voltage necessary to ensure output regulation can be calculated as: equation 8 where r ds(on)_hs_max is the maximum high side resistance and rl is the series inductor resistance. 5.2 pgood (power good output) the device also features a power good output signal. the v fb pin is internally connected to a comparator with a threshold set at 90% of the reference voltage (0.6 v). since the output voltage is connected to the v fb pin by a resistor divider, when the output voltage goes lower than the regulated value, the v fb pin voltage goes lower than 90% of the internal reference value. the internal comparator is triggered and the power good pin is pulled down. the pin is an open drain output, so it should be connected to a pull up resistor. if the feature is not required, the pin can be left floating. 5.3 adjustable output voltage the output voltage can be adjusted by an external resistor divider from a minimum value of 0.6 v up to the input voltage. the output voltage value is given by: v in min ? v o i o r ds on () hs ? max ? r l + () ? + =
AN2115 synchronization doc id 11165 rev 5 17/33 equation 9 thanks to the very low fb leakage current (25 na), high r 3 and r 2 values can be chosen (hundreds of k ) which increase system e fficiency at very low load. 5.4 ovp (overvoltage protection) the device is equipped with an internal overvoltage protection circuit to protect the load. if the voltage at the feedback pin goes higher than an internal threshold set at 10% (typ.) higher than the reference voltage, the low side mosfet is turned on until the feedback voltage goes lower than the reference voltage. during overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also able to sink current. 5.5 thermal shutdown the device also has thermal shutdown protection, which is activated when the junction temperature reaches 155 c. in this case both the high and low side mosfets are turned off. once the junction temperature goes back below 95 c, the device resumes normal operation. v out 0.6 1 r 3 r 2 ------ - + ?? ?? ? =
application information AN2115 18/33 doc id 11165 rev 5 6 application information 6.1 external component selection 6.1.1 input capacitor the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. the rms input current (flowing through the input capacitor) is: equation 10 where is the expected system efficiency, d is the duty cycle and i o is the output dc current. assuming = 1, this function reaches its maximum value at d = 0.5 and the equivalent rms current is equal to i o /2. the maximum and minimum duty cycles are: equation 11 equation 12 depending on the output voltage value, the worst case could occur when the input battery is nearly discharged. usually the best choice for the input capacitor is the mlcc (multi layer ceramic capacitor) thanks to its very small size and very low esr. ta bl e 3 provides a list of some mlcc manufacturers. 6.1.2 output capacitor the output capacitor is very important for satisfying the output voltage ripple requirement. very small inductor values reduce the size and cost of the application but increase the current ripple. table 3. recommended input capacitors manufacturer series cap value (f) rated voltage (v) esr@1.4 mhz (m ) panasonic ecj 10 to 22 6.3 10 taiyo yuden jmk 10 to 22 6.3 10 murata grm 10 to 22 6.3 5 to 10 i rms i o d 2d 2 ? --------------- - ? d 2 2 ------ - + ? = d max v o v inmin ----------------- = d min v o v inmax ------------------ - =
AN2115 application information doc id 11165 rev 5 19/33 this ripple, multiplied by the esr of the output capacitor, is the output voltage ripple. tantalum and ceramic capacitors are usually good for this purpose. ceramic capacitors have the minimum esr for a given size, so for very compact applications they are the best choice. poscap capacitors from sanyo are also a good choice for the output filter. the list below provides some capacitor manufacturers. 6.1.3 inductor the inductor value establishes the ripple current flowing through the output capacitor. the ripple current is usually fixed at 20% - 40% of the output current, an approximation of which is obtained with the following formula: equation 13 for example, with v out = 3.3 v, v in = 4.2 v (li-ion battery fully charged), f sw = 1.4 mhz, i o = 600 ma and i = 200 ma, the inductor value is about 3.3 h. the peak current through the inductor is given by: equation 14 note that if the inductor value decreases, the peak current (which must be lower than the current limit of the device) increases. this peak current must be lower than the saturation current of the choke. this is particularly important when using ferrite cores because they can saturate severely. the inductance value decreases abruptly when the saturation threshold is exceeded, thus causing an abrupt increase in the current flowing through it. the inductor should be sele cted with system stability taken into consideration (see the paragraph regarding slope compensation). parasitic resistance should also be considered when selecting the inductor, as too high a value can decrease efficiency. in the following table some inductor manufacturers are listed. table 4. recommended output capacitors manufacturer series cap value (f) rated voltage (v) esr (m ) panasonic ecj 10 to 47 6.3 10 panasonic eef 22 to 47 6.3 60 to 90 taiyo yuden jmk 10 to 47 6.3 10 sanyo poscap tpa 47 to 100 6.3 80 to 100 murata grm 10 to 22 6.3 5 to 10 l v in v out ? () i ------------------------------ t on ? = i pk i o i 2 ----- + =
application information AN2115 20/33 doc id 11165 rev 5 6.1.4 compensation network (r 1 c 3 ) as shown in section 4.3 the system stability ca n be studied using the loop transfer function given by equation 3 . if the output capacitor is of the ceramic type, the zero due to the esr will generally be outside of the system bandwid th. thus, the stability of the system will be ensured by the cancellation between the pole due to the output capacitor, the equivalent load and the r 1 c 3 zero. equation 15 represents a simplified gain loop expression, applicable around the transition frequency f t : equation 15 assuming that c 2 = 10 f, the transition frequency at 0 db = 30 khz (f t is equal to the system bandwidth), and the output voltage = 1.8 v, the value of r1 can be calculated as: equation 16 the nearest standard e12 series value is r 1 = 24 k . the higher the bandwidth , the faster the transient respon se will be, but the bandwidth (and so the r 1 value) must be lower than f sw /10 to avoid being influenced by the sampling effect poles as mentioned in section 4.3 . the zero due to the compensation network must be at the least 5 times before th e frequency transition, so the value of c3 will be: equation 17 the nearest standard value is c 3 = 220 pf table 5. recommended inductors manufacturer series inductor valu e (h) saturation current (a) coilcraft do1607c 6.8 to 15 0.72 to 0.96 dt1608c 6.8 to 15 0.6 to 1 lpo1704 6.8 to 10 0.8 to 0.9 ch4192-a 4.7 1.3 do1606t 6.8 to 10 1 to 1.1 panasonic ell6rh 6.2 to 22 0.7 to 1.4 ell6gm 6.8 to 10 0.93 to 1.1 to ko d62cb 10 to 22 0.71 to 1.07 d62c 10 to 22 0.63 to 0.99 coiltronics sd10 3.3 to 6.2 0.92 to 1.31 sd12 3.3 to 6.2 1.08 to 1.42 g loop s () g m r 1 sc 2 ------------------ - = r 1 2 f t c 2 g m ------------------- 24k = = c 3 5 2 f t r 1 ------------------- 220pf = =
AN2115 application information doc id 11165 rev 5 21/33 if the output capacitors are of the tantal um type, the esr zero is within the system bandwidth and it can be used to stabilize th e system so that th e zero due to the compensation network will be rendered unnecessary. 6.2 application los ses and efficiency there are many losses affecting the efficiency of the application. some of these losses are related to the device and others are related to the external components. the most important losses are described below. 6.2.1 conduction losses these losses are basically due to the significant resistances of the internal switches and the external inductor. usually the current ripple across the inductor is negligible and so to estimate the conduction losses of the inductor, the average output current can be considered. the conduction losses of the switches depend also on the duty cycle of the application. the rms current flowing through the high side mosfet is (i o ) 2 d, while the rms current flowing through the low side mosfet is (i o ) 2 (1-d). so, the total conduction losses of the application are: equation 18 where r on-hs and r on-ls are the series resistances of the high side and low side mosfets respectively, and r l is the series resistance of the inductor. the conduction losses due to the esr of the input and output capacitors are usually negligible, particularly when using ceramic caps (very low esr). in any case, when the esr values for these caps are high, their conduction losses are: equation 19 where i is the current ripple flowing through the choke and d the duty cycle of the application. the conduction losses are particularly important at high current cause they depend on its squared value. 6.2.2 switching losses the switching losses are due to the turning on and off of the internal high side mosfet. equation 20 where t on and t off are the turn on and turn off times of the internal high side switch. these are approximately in the range of 15 ns to 20 ns.this loss is important at high frequency. p mos i o 2 r on hs ? d () r on ls ? 1d ? () r l + ? + ? () ? = p cin cout , i o 2 d1d ? () ? () esr cin i 2 12 -------- + ? ? esr cout ? = p switching v in i o ? f sw ? t on t off + () 2 ----------------------------------- - ? =
application information AN2115 22/33 doc id 11165 rev 5 6.2.3 gate charge losses the gate charge losses derive from switching the gate capacitance of the internal mosfets. the gate capacitances (c h for the high side mosfets and c l for the low side mosfets) are charged and discharged with the input voltage at the switching frequency. equation 21 these losses are also directly proportional to the switching frequency and input voltage but are usually negligible co mpared with the conduction and switching losses. 6.2.4 thermal consideration depending on the application conditions (input voltage, switching frequency, output current) and ambient temperature, the heat produced by device losses could increase the junction temperature to over its absolute maximum rating. the following equation can estimate the junction temperature of the device: equation 22 where t a is the ambient temperature of the application, r th_ja is the thermal resistance junction to ambient of the package and p tot is the overall power dissipated by the device. r th_ja depends to some degree on the application board but it can considered approximately equal to 180 c/w. p tot given by: equation 23 figure 13. thermal perf ormance results: v in = 3.7 v, v out = 1.8 v, i out = 800 ma the figure above shows the thermal performance of the device mounted on the application board, which is described in the following paragraph. p gate change ? v in 2 c h c l + () ? f sw ? = t j t a r th ja ? p tot ? + = p tot p mos p switching p gate charge ? ++ =
AN2115 application information doc id 11165 rev 5 23/33 figure 14. r ds(on) vs. temperature to more accurately estimate the power dissipated, it may be useful to observe the variation with the temperature of the mosfet?s r ds(on) , as shown in the figure 14 .
application board AN2115 24/33 doc id 11165 rev 5 7 application board 7.0.1 demonstration board the illustrations below show the layo ut of the demons tration board. figure 15. component placement figure 16. top side view figure 17. bottom side view
AN2115 demonstration board schematic doc id 11165 rev 5 25/33 8 demonstration board schematic the very small package and high switching frequency allow for a very compact application. the demonstration board circuit is shown in figure 18 : figure 18. schematic of the demonstration board the external component parts list is shown below: table 6. demonstration board parts list reference part number description manufacturer c1 grm21br60j106ke19 10 f 6.3 v murata c2 grm21br60j106ke19 10 f 6.3 v murata c3 c0406c221j5gac 220 pf, 5% 50 v kemet r1 10 k 1% 0402 neohm r2 100 k 1% 0402 neohm r3 200 k 1% 0402 neohm r4 100 k 1% 0402 neohm l1 ch4192-a 4.7 h coilcraft lps4012-472mlc 4.7 h
efficiency results AN2115 26/33 doc id 11165 rev 5 9 efficiency results some efficiency resu lts are shown in the figures below. figure 19. low noise vs. low consumption efficiency figure 20. efficiency vs. output current
AN2115 efficiency results doc id 11165 rev 5 27/33 figure 21. efficiency vs. output current figure 22. efficiency vs. output current
application ideas AN2115 28/33 doc id 11165 rev 5 10 application ideas 10.1 buck boost topology in portable applications, the input voltage chan ges significantly due to the battery discharge profile, which often depends on parameters like temperature, discharge rate, battery ageing, etc. moreover, in certain applications the output voltage requirements can also change. this could imply that is not possible to provide the desired regulated output voltage using a simple buck topology. this problem is often present, for example, in systems using a single li-ion cell, whose voltage profile changes from 4.2 v down to 2.7 v or less. in fact, in these systems, a 3.3 v output is normally required to power the processor i/o, memory and logic. adopting the buck topology, the 3.3 v output can be regulated until the battery voltage is approximately 3.4 v, depending also on the minimum dropout of the regulator. depending on the battery type and conditions, this would leave unused some 20 - 40% of its capacity. another even more critical application is the power management of 3g phones, where 3.7 v or more can be required to power the rf power amplifier (pa). in order to use the full battery capacity in these applications, a positive buck boost topology can be used. figure 23 shows how to implement this topology using the l6928. this topology may be more suitable than a standard buck, depending on the battery discharge profile and the load conditions. in fact, the efficiency loss of the buck boost topology can be translated into an equivalent loss in battery capacity. this can then be compared with the gain in battery capacity due to the fact that it is used over the full voltage range. figure 23. positive buck boost applicat ion. 1 li-ion cell to 3.3 v@0.25 a 10.2 white leds white leds are now widely used both for lcd backlighting and for illumination. since their brightness is proportional to the current flowing through them, a current control loop must be implemented rather than a voltage control loop. the l6928 can be used in a current control architecture by simply inserting a sense resistor between the fb and gnd pins and connecting the led in series with it. the loop will set 0.6 v across th e sense resistor and thus a constant current flow through the led. the current, and therefore the brightness, can be adjusted by changing the resistor value or the voltage across it (by partitioning the fb pin
AN2115 application ideas doc id 11165 rev 5 29/33 voltage). the forward voltage across a white led is approximately 3.6 v and so, depending on the input source, appropriate topologies must be used. 10.2.1 driving white leds: buck topology the simple buck topology can be used when the input voltage source is higher than approximately 4.5 v, which is the case, for example, with a usb bus. figure 24. buck led in this case, the maximum device current (800 ma, continuous) can be delivered to the led. moreover, in this topology the efficiency is maximized. 10.2.2 driving white leds: boost topology when the input voltage source is always lower than 3 v (which is the case, for example, of 2 nimh battery cells) a boost topology must be implemented, as shown in figure 25 . figure 25. boost led in this case, according to the boost topology, the maximum current that can be delivered depends on the duty cycle. the relation between the output current and the internal switch current (assuming a negligible current ripple and 100% efficiency) is given in equation 24 :
application ideas AN2115 30/33 doc id 11165 rev 5 equation 24 this topology is possible only because the input source is a battery, and so it must not be referred to ground. a drawback of this approach, which is intrinsic in the boost topology, is that a path between the input and output is always present. this does not allow effective short circuit pr otection and can generate a battery discharge even when the device is turned off. 10.2.3 driving white l eds: buck boost topology when a single li-ion cell is used at the input, a buck boost topology can be employed, as shown in figure 26 . figure 26. buck boost led the relationship between the output current and the switch current is the same as in the boost topology. an advantage of this topology compared with the boost topology, however, is that when the device is turned off there is no current path between the input and the output. this allows effective short circuit protecti on and minimizes the current drawn from the battery when the device is turned off. a dimming control can be developed by turning the device on and off with a frequency of around 100 - 200 hz in order to avoid led flickering figure 27 . another way to implement led dimming is by changing the voltage of the dimming resistor figure 28 . i out i switch 1d ? () =
AN2115 application ideas doc id 11165 rev 5 31/33 figure 27. led dimming control using pwm figure 28. analog led dimming control both solutions change the output current by changing the fb voltage. in figure 28 a dc voltage is used. in figure 27 the average voltage coming fr om the pwm signal is utilized.
revision history AN2115 32/33 doc id 11165 rev 5 11 revision history table 7. document revision history date revision changes jan-2005 1 first issue 06-aug-2007 2 added list of figures , minor text changes 28-nov-2007 3 changed figure 14 26-feb-2009 4 modified: section 6.1.1 and ta bl e 6 (reference 3) 23-mar-2011 5 added: l1 part number table 6 on page 25
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